The present invention relates to a digital testing system for high frequency digital Phase-Locked Loops (PLLs). This application is related to U.S. patent application Ser. No. 07/729,937, entitled "Digital Serial Loop Filter for High Frequency Control Systems" U.S. patent application Ser. No. 07/681,095, entitled "Digital Signed Phase to Frequency Converter for High Frequency Phase-Locked Loops", as well as U.S. patent application Ser. No. 07/730,228, describing a phase detector, U.S. patent application Ser. No. 07/,731,138 describing a phase error processor, and U.S. Pat. No. 5,132,633 describing a frequency controlled oscillator, all incorporated herein by reference for all purposes.
Testing of dynamic performance parameters of PLLs, at very high frequencies, requires time measurements in sub-nSeconds (e.g. clock jitter for 125 MHz PLLs would be on the order of 0.75 nS). Due to limited resolution, most automatic test equipment is not capable of making such measurements. This has made the dynamic testing of high frequency PLL performance parameters, at component level or at board level, a high-price-tag item for most manufacturers. Furthermore, volume testing has also been considered as difficult to achieve if these products are to remain price competitive. Therefore, the general approach in the industry has been one of "guaranteed by design" with ac/dc tests at the integrated circuit level and limited functionality tests at board level.
From the above it is seen that an improved device/method for PLL testing is desired.